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TRH031M datasheet www.3alogics.com | datasheet | scope this technical document contains 3alogics 13.56mhz multi-protoc ol reader ic (TRH031M) features and structure. related 3alogics document trh03xm cookbook firmware user manual application access control / home network & digital door lock pos terminal / public transportation electronic library / intelligent toys e-parking / product authentication distribution, logistics 1 confidential
TRH031M datasheet 2 ww.3alogics.com confidential | w revision history date version content 2007. 01. 29 3.01 old version data sheet ( register initial value and address modification) 2008. 01. 16 3.1 new version data sheet preliminary release 2008. 04. 29 3.3 3.3 version release notice : all referenced brands, p roduct names, service name and trademarks are the property of their respective owners. any read? - is a trademark of 3alogics. copyright ? 2008 3alogics inc. this draft document is a copyright-protected by 3alogics. excep t as permitted under the applicable laws of the users country, neither this draft docum ent nor any extract from it may be reproduced, stored in a retrieval system or transmitted in a ny form or by any means, electronic, photocopying, record ing or otherwise, without prior written permission. disclaimer 3alogics accepts no liability for the content of this document, or for the consequences of any actions taken on the basis of the information provided, unless that information is subsequently confirmed in writing. if you are not the intended recipient you are notified that disclosing, copying, distributing or taking any action in reliance on the contents of this information is strictly prohibited. contact 3alogics inc. 7 th floor, hyundai-office bldg., 9-4, sunae-dong. bundang-gu, seongnam-si, gyeonggi-do, 463-783,korea tel : (82)-(31)-715-7117 fax : (82)-(31)- 719-7551 homepage: http://www.3alogics.com e-mail : rfid@3alogics.com printed in the republic of korea.
TRH031M datasheet www.3alogics.com | confidential 3 document contents chapter1 introduction ...................................................................................................................... 6 1.1 f eatures ............................................................................................................................................................................6 1.2 b lock d iagram ...............................................................................................................................................................7 1.3 p in d iagrams ..................................................................................................................................................................8 1.4 p in d escription ..............................................................................................................................................................9 1.5 s pecial f unction r egister g roup ......................................................................................................................... 10 1.6 s pecial f unction r egister g roup (c ontinue ) .............................................................. .................................... 11 chapter2 TRH031M functionality ................................................................................................ 12 2.1 i ntroduction .............................................................................................................................. ................................. 12 2.2 rfid r eader ............................................................................................................................. .................................... 12 2.3 r ole of TRH031M ............................................................................................................................. ........................ 13 2.3.1 modulation / demodulation ........................................................................................................................ 13 2.3.2 encoding / decoding .............................................................................................................................. ........ 14 2.3.3 framing .............................................................................................................................. ................................... 15 2.3.4 data integrity ............................................................................................................................. ........................ 15 2.3.5 timer and interrupt ............................................................................................................................. ............ 16 chapter3 host interface ................................................................................................................. 17 3.1 i ntroduction .............................................................................................................................. ................................. 17 3.2 p arallel i nterface .............................................................................................................................. ........................ 17 3.2.1 using dedicated address .............................................................................................................................. 18 3.3 p arallel i nterface h ardware c onfiguration .............................................................. .................................... 19 3.4 spi s erial i nterface ............................................................................................................................. ...................... 20 3.4.1 spi serial interface hardware configuration .............................................................. .......................... 21 3.4.2 spi serial interface data format ............................................................... ................................................. 22 chapter4 command ............................................................................................................................ 2 4 4.1 i ntroduction .............................................................................................................................. ................................. 24 4.2 c ommand e xplanation ............................................................................................................................. ............... 24 4.3 t ransmit /r eceive s tatus c heck ............................................................................................................................. 26 4.4 c ontrol ............................................................................................................................. ........................................... 28 4.5 e rror c heck .............................................................................................................................. ................................... 29
TRH031M datasheet 4 ww.3alogics.com confidential | w chapter5 protocol ............................................................................................................................. 30 5.1 i ntroduction .............................................................................................................................. ................................. 30 5.2 t ransmit d ata f ormat s elect .............................................................................................................................. .. 30 5.3 r eceiver d ata f ormat s elect .............................................................................................................................. .... 32 5.3.1 receive delay time .............................................................................................................................. ............ 34 5.3.2 bit level receiving ............................................................................................................................. .............. 34 5.4 a nti -c ollision ............................................................................................................................. ............................... 35 5.4.1 collision detection .............................................................................................................................. ............. 35 5.5 b it l evel data t ransmit /r eceive ............................................................................................................................ 3 7 5.6 p rotocol .............................................................................................................................. ......................................... 39 5.6.1 iso/iec 14443a protocol ............................................................................................................................. . 39 5.6.2 iso/iec 14443b protocol .............................................................................................................................. . 41 chapter6 fifo buffer .......................................................................................................................... 43 6.1 i ntroduction .............................................................................................................................. ................................. 43 6.2 fifo b uffer d ata i nput /o utput ............................................................................................................................ 4 3 6.3 fifo b uffer r elated f unctions ............................................................................................................................ 44 6.3.1 fifo buffer data deletion ............................................................................................................................ 44 6.3.2 fifo buffer error .............................................................................................................................. ................. 44 6.3.3 fifo buffer caused interrupt ....................................................................................................................... 44 chapter7 signal integrity .............................................................................................................. 46 7.1 i ntroduction .............................................................................................................................. ................................. 46 7.2 s ignal i ntegrity s etting m ethod ......................................................................................................................... 46 chapter8 interrupt ............................................................................................................................ 49 8.1 i ntroduction .............................................................................................................................. ................................. 49 8.2 i nterrupt u se m ethod ............................................................................................................................. ................ 49 chapter9 power management ...................................................................................................... 52 9.1 i ntroduction .............................................................................................................................. ................................. 52 9.2 p ower down m ode e ffect .............................................................................................................................. ........ 52 9.3 p owerdown m ode d irections ............................................................................................................................. . 53 9.3.1 hardware powerdown mode ...................................................................................................................... 53 9.3.2 software powerdown mode ........................................................................................................................ 53
TRH031M datasheet www.3alogics.com | confidential 5 chapter10 timer ................................................................................................................................... 54 10.1 i ntroduction ............................................................................................................................. ............................... 54 10.2 t imer s etting ............................................................................................................................. ............................... 54 10.3 t imer f unction .............................................................................................................................. ........................... 56 chapter11 analog .............................................................................................................................. . 57 11.1 t ransmitter .............................................................................................................................. ................................. 57 11.2 t ransmitter s tructure .............................................................................................................................. ............ 57 11.3 t ransmitter f unction ............................................................................................................................. .............. 57 11.3.1 tx1 and tx2 function setting .................................................................................................................. 58 11.3.2 tx1 and tx2 ou tput power setting ............................................................... ........................................ 60 11.3.3 tx1 and tx2 modu lation index adjustment ............................................................... ....................... 61 11.3.4 recognition distance and power consumption .............................................................. ................. 61 11.4 r eceiver .............................................................................................................................. ......................................... 62 11.5 r eceiver s tructure .............................................................................................................................. .................... 62 11.6 r eceiver f unctions ............................................................................................................................. .................... 63 11.6.1 envelope detector ............................................................................................................................. ............ 63 11.6.2 offset collection .............................................................................................................................. ............... 63 11.6.3 variable gain amplifier: vga .................................................................................................................... 63 11.6.4 comparator ............................................................................................................................. ......................... 64 chapter12 test ...................................................................................................................................... 66 12.1 i ntroduction ............................................................................................................................. ............................... 66 12.2 h ow to use test pin ............................................................................................................................. ................... 66 chapter13 electric al characteristics ...................................................................................... 68 13.1 o perating condition range ............................................................................................................................. .... 68 13.2 c urrent consumption ............................................................................................................................. .............. 68 13.3 s tandard i/o p in dc characteristics ............................................................... ............................................... 69 13.4 s chmitt t rigger i nput t hreshold ...................................................................................................................... 69 13.5 t iming specification .............................................................................................................................. .................. 70 13.5.1 timing for read/write strobe .................................................................................................................. 70 13.5.2 timing for spi compatible interface .............................................................. ........................................ 71 13.6 p ackage i nformation ............................................................................................................................. ................ 72
TRH031M datasheet 6 ww.3alogics.com confidential | w chapter1 introduction 1.1 features basic information - 13.56mhz multi-protocol rfid reader chip - 3.3v operation voltage - 32pin lqfp package supported protocols: - iso/iec 14443 a/b type, iso/iec 15693 - ta g - i t ( te x a s i n s t r u m e n t ) performs analog and digital mixe d operation as standards indica ted - modulation/demodulation, encoding/decoding - framing and collision dete ction for anti-collision - automatic data integrity check functions for microprocessor interface - 64 bytes fifo buffer for immediate data storage - 4 types of parallel interfac e and spi serial interface - configurable interrupt can inform event to microprocessor - configurable and adjustable timer function can cooperated wit h transceive state and interrupt power consumption minimization - hardware/software power down function - minimized leakage and stand-by current other functions - transmit power and modul ation index configuration - two transmit drivers can be configured - adjustable receiver sensitivity depends on noise condition - data rate and pulse width configuration according to protocol standards - test pins for operation check
TRH031M datasheet www.3alogics.com | confidential 1.2 block di agram picture 1-1 displays TRH031M blo ck diagram that is divided by d igital and analog parts. picture 1-1 TRH031M block diagram 7
TRH031M datasheet 1.3 pin diagrams 8 ww.3alogics.com confidential | w picture 1-2 TRH031M pin diagrams
TRH031M datasheet www.3alogics.com | confidential 9 1.4 pin description table 1-1 TRH031M pin map number pin name description direction 1 testout test output (for factory test) output 2 testin test input (for factory test) input 3 wrb write bar (active low) input 4 rdb read bar (active low) input 5 xout crystal oscillator output output 6 xin crystal oscillator input input 7 dvss digital ground ground 8 dvdd digital power power 9-16 data <0:7> 8-bit data bus inout 17-19 addr <0:2> 3-bit address bus input 20 pale positive address latch enable (active high) input 21 irq interrupt request output 22 rst reset (active high) input 23 avdd analog power power 24 avss analog ground ground 25 test2o test output (for factory test) output 26 rx receiver input (analog) input 27 vmid receive reference voltage (analog) output 28 csb chip select bar (active low) input 29 tx1 transmit driver #1 (analog) output 30 tvdd transmitter power power 31 tx2 transmit driver #2 (analog) output 32 tvss transmitter ground ground
TRH031M datasheet 10 ww.3alogics.com confidential | w 1.5 special function register group table 1-2 TRH031M special function register group 1 address name value 0x00 page usepage pageselect 0x01 command command 0x02 fifodata fifodata 0x03 status1 modemstate irq err hialert loalert 0x04 fifolength f i f o l e n g t h 0x05 status2 trunning lockstatus terrflag tadflag rxlastbits 0x06 ien setien timerien txien rxien idleien hialertien loalertien 0x07 irq setirq timerirq txirq rxirq idleirq hialertirq loalertirq 0x08 rfu 0x09 control powerdown tstopnow tstartnow flushfifo 0x0a errflag fifoovfl crcerr parityerr collerr 0x0b collpos collpos 0x0c timervalue timervalue 0x0d crcresultlsb crcresultlsb 0x0e crcresultmsb crcresultmsb 0x0f bitframe rxalign tmaskflag txlastbits 0x10 rfu 0x11 txcontrol modulatorsource f100ask tx2inv tx2cw tx2rfen tx1rfen 0x12 cwconductance cwconductance 0x13 modconductance modconductance 0x14 codcontrol ti_addr txcoding 0x15 modwidth m o d w i d t h 0x16 rfu 0x17 bframing eofwidth charspacing sofwidth 0x18 rfu 0x19 rxcontrol1 vgagain 0x1a decodcontrol zrafcoll rxframing 0x1b rfu 0x1c rxthreshold cro hyr crv
TRH031M datasheet www.3alogics.com | confidential 11 1.6 special function register group (continue) table 1-3 TRH031M special function register group 2 address name value 0x1d rfu 0x1e rxcontrol2 adcdmd dcdsrc 0x1f rfu 0x20 rfu 0x21 rxwait r x w a i t 0x22 redundancy crcwr crcb rxcrcen txcrcen parityodd parityen 0x23 crcpresetlsb crcpresetlsb 0x24 crcpresetmsb crcpresetmsb 0x25 rfu 0x26 testoutsel testsel 0x27 rfu 0x28 rfu 0x29 fifolevel w a t e r l e v e l 0x2a timerclk trestart tprescaler 0x2b tcontrol tstoprxend tstoprxbe tstarttxend tstarttxbe 0x2c treloadvalue treloadvalue 0x2d irqconfig i r q i n v 0x31 rfu 0x32 rfu 0x33 rfu 0x3a rfu
TRH031M datasheet chapter2 TRH031M functionality 2.1 introduction this chapter will explain rfid communication process and role o f TRH031M instead of detailed functions of trh31m. 2.2 rfid reader picture 2-1 rfid reader picture 2-1 displays 13.56mhz rfid reader structure using trh03 1m. as displayed on picture, TRH031M is placed between antenna and microprocessor. TRH031M, from microprocessor, receives both command and data per each protocol format to tag through a ntenna. receiving process works conversely. TRH031M converts data from the antenna by dig itizing, and microprocessor verifies data received from TRH031M. therefore, microprocessor communicates with rfid tag through TRH031M. in other words, TRH031M provides wireless comm unication inter face between microprocessor and rfid tag. 12 ww.3alogics.com confidential | w
TRH031M datasheet www.3alogics.com | 2.3 ro le of TRH031M 2.3.1 modulation / demodulation picture 2-2 modulation / demodulation 13 confidential key functions of TRH031M are modulation and demodulation. modul ation is sending data through carrier (as seen on picture 2-2 from b to a). demodulat ion is conversely receiving signal (such as a on picture 2-2) by removing carrier and converting t o b. therefore, modulation occurs in transmit mode (tx) and demodulation occurs in receiving mode (rx).
TRH031M datasheet 2.3.2 encoding / decoding picture 2-3 is an example of iso 14443a type tag and reader enco ding/decoding signal. encoding/decoding process differs by different protocol used; therefore, detailed information should follow standard specification. encoding is creating waveform (seen as picture 2-3(a) or 2-3(c)) for data transmission and decoding is process of distinguishing waveform (seen as picture 2-3(a) or picture 2- 3(c)) as data 0 or data 1. first, decoding process is as follows. from analog part, demodulation completed signal is shaped as picture 2-3(a) and picture 2-3(c). picture 2-3 encoding / decoding as seen in picture 2-3(a) and picture 2-3(c), carrier is eliminated but subcarrier remains. thus, eliminate subcarrier. from picture 2-3(a) to picture 2-3(b) tra nsformation process and picture 2-3(c) to picture 2-3(d) transformation process are subcarrier elimination process. eliminated subcarrier signal (seen as picture 2-3(b) and picture 2-3(d)) will take sh ape of manchester coding. TRH031M digital part in the end finish t he data decoding process by dis tinguishing the signal (picture 2-3(b)) as data 0 and (picture 2-3(d)) as data 1. in case of encoding, conversely, transmit data value stored in fifo will impact the shape as seen on picture 2-3(a) and picture 2-3(c). all these processes will be performed automatically when user selects protocol type. 14 ww.3alogics.com confidential | w
TRH031M datasheet www.3alogics.com | 2.3.3 framing picture 2-4 framing picture 2-4 displays iso 14443a frame structure. framing means simply making frame. frame is data transmission unit in communication and word packet is us ed very frequently. frame structure differs based on each protocol, and TRH031M performs framing on ce user selects protocol type. frame structure is simply divided into sof (start of frame) and eof (end of frame). for iso14443a, parity is included aft er 8-bit data for data integri ty. 2.3.4 data integrity data integrity signifies data er ror status durin g transmission. to check data integrity, ordinary protocols during transmit/receiving mode attaches surplus data for error checking. crc is one of the major errors checking method. TRH031M has hardware check ca pability for crc, parity error status check for data integrity during wireless interface. as o ther features, error checking is performed automatically by setting couple of features and resul t is sent to microprocessor through register. 15 confidential
TRH031M datasheet 2.3.5 timer and inte rrupt rf signal not modulated tx signal demodulated rx signal (a) (b) (c) interval tx end rx start picture 2-5 status of tx/rx signal interrupt and timer instruction is not fixed. user can improve program efficiency by using timer and interrupt. the following is an example of program using interrupt and timer. picture 2-5 is end of tx and beginning of rx in rfid communicat ion. picture 2-5(a) is analog signal waveform from antenna, and picture 2-5(b) is a signal tr ansmitting from digital part to analog part for modulation after encoding. picture 2-5(c) is a received signal from analog part after demodulation. as seen on pi cture 2-5, there is a time del ay between ending tx and beginning rx. also tx and rx do not occur normally because it i s not possible to receive response when tag is outside of antenna recognition distance. t herefore, software is developed for normal transmission, TRH031M will idle waiting for receiving si gnal when no response from tag. consequently, timer and interrupt should be used in case failed receiving signal after transmission. 16 ww.3alogics.com confidential | w from above example using receiving interrupt and timer interrup t, if completing receiving it activates receiving interrupt. if signal is not received in giv en time, timer interrupt occurs. for these action to happen, set from ien(0x06) to use timer interrupt and receive interrupt and set treloadvalue to applicable distance interval (picture 2-5). las tly, set tcontol(0x2b) register to tstarttxend, thereafter, set the timer to count after signal tr ansmission. from microprocessor normal completion of transmitting and receiving can be determined very simply by type of interrupt generated after complet ion of transmitting and receiv ing.
TRH031M datasheet www.3alogics.com | chapter3 host interface 3.1 introduction host typically means microprocessor. TRH031M supports 4 types o f parallel interface and spi serial interface to host. 3.2 pa rallel interface TRH031M supports total of 4 types of parallel interface. all 4 interfaces support 8 bit data bus differentiated by read/write exec ution methods and allotted address methods. user can select any one of 4 interfaces that is more convenient and efficient. pict ure 3-1 displays 4 interface types supported by TRH031M. picture 3-1 shape of TRH031M supported microprocessor interface 17 confidential
TRH031M datasheet there is 2 ways to delivery address. picture 3-1(a) and picture 3-1(b) display the difference of multiplexed addressing and dedic ated addressing. when using mul tiplexed addressing (picture 3- 1(a)), address is delivered through data bus. when address is r ead is determined by pale pin. dedicated addressing is used by dividing data bus and address b us. instead of using pale pin, address is controlled by wrb and rdb pin. picture 3-1(c) and picture 3-1(d) are differences of common mod e control method and separated mode control method. differences of two methods are h ow to designate read and write using two pins, wrb and rdb in common mode, wrb value bei ng high implies read and low value implies write . also in common mode, read/write point is indicated when rdb fa lls to low value in either read/write situation. for separate mode, re ad/write is allotted in each pin. wrb falling to low value means write, and rdb falling to low va lue means read. 3.2.1 using dedicated addr ess using dedicated address, address line constitutes in 3 bits, th us, not able to designate all TRH031M memory map having total 6 bits. therefore, TRH031M util izes low level 3 bits of page(0x00) register to designate upper level 3 bits of address. msb of page(0x00) register is set to 1 when using page(0x00) register low level bit for address. page(0x00) register value is to set addr pin to all 0 and write. picture 3-2 dedicated address configuration 18 ww.3alogics.com confidential | w picture 3-2 displays dedicated a ddress configuration. addr impl ies data entered from TRH031M input pin, and address im plies to TRH031M last used add ress.
TRH031M datasheet www.3alogics.com | confidential 19 table 3-1 page register name address reset value page 0x00 0x80 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit usepage 0 0 0 0 pageselect number name description 7 usepage 0: the pageselect is not in use for register address se tting. 1: the pageselect is in use for register address setting. 2-0 pageselect if usepage value is 1 , upper level of register addre ss 3 bit pageselect value is used. 3.3 pa rallel interface hardware configuration parallel interface are divided into 4 different types by addres s allocation methods and control signal use methods. however, difference in control methods do n ot impact hardware configuration. whether user selects separated mode or common mo de, hardware configuration is the same and control method is determined using software. TRH031M control method is based on first executed write command a fter reset. basically if sepa rated mode is used to write after reset then until next reset separ ate mode is used continuously. hardware configuration for address delivery method is as below. in case of dedicated address, pale pin is not used. in multip lexed, addr pin is not used. t able 3-2 displays each value when not using pale or addr. table 3-2 allocation of signal based on addressing methods pin name dedicated address bus multiplexed address bus pale high pale addr2 addr2 low addr1 addr1 high addr0 addr0 high
TRH031M datasheet 3.4 spi seri al interface TRH031M also supports spi serial interface in addition to para llel interface. spi (serial peripheral interface) can send and receive data through 3 to 4 bus lines. TRH031M is ideal for small quantity bus control or control many TRH031Ms with one mi croprocessor. spi is divided by master and slave. master gives commands from spi protocol and s lave follows the commands. TRH031M functions as slave during communication. spi clock (sck) is created by ma ster, and use mosi (master-out slave-in) during communication from master to slave and miso (m aster-out slave-in) during comm unication from slave to master. nss (negative slave select) is similar to chip select being use d during one master controlling multiple slaves and wanting to s elect specific slave to set com mand. nss mosi sck msb 20 ww.3alogics.com confidential | w miso msb 6-bit 5-bit 1-bit lsb slave read point start point end point data transition picture 3-3 spi serial interface operation picture 3-3 displays 1 byte (8bit) delivery process using spi i nterface. to initiate spi communication, first nss need to change to low value. msb of m iso begins output from negative edge of nss. then, mosi signal transfers from master to slave. slave reads mosi signal from positive edge of sck. up to this point is the process of 1 bit data transaction. basically from positive edge of sck enter 1 bit of data from ma ster to slave, and from negative edge of sck and negative edge of nss slave outputs 1 bit of dat a to master. this process is repeated 8 times to send and receive 8 bits of data and completes 1 byte transaction. to send or receive more than 1 byte of data, maintain nss to low and se nd and receive by byte. after all data is sent nss returns to high value.
TRH031M datasheet www.3alogics.com | 3.4.1 spi serial interface hardwar e configuration spi interface, unlike parallel interface, is determined during reset process. therefore, to use spi modes, before sending reset signal assign inputs as below table 4-2. table 3-3 spi spi interface configuration 21 confidential pin name spi interface pale nss addr2 sck addr1 low addr0 mosi rdb high wrb high csb low data7 data1 1100001 data0 miso
TRH031M datasheet 3.4.2 spi serial interface data format picture 3-4 displays spi command structure (example: master rea ding 4 registers). when executing read command, master m ust send to slave the register address wanted to read. end byte is dummy thus to read 4 registers 5 bytes are entered. con sequently, to read n number of registers, user must enter n+1 number of bytes. typically dummy uses 8 continuous 0 values. one additional point of caution is that after address input, da ta output occurs when next byte is entered. as seen in th e picture, when addr1 is entered data0 o utput occur not data1. in write command there is not output through miso, but through mosi, address and data types of signal should be entered. entry steps are first byte recognizes as address, and before nss becomes high, previously ent ered bytes are recognized as da ta. from the picture, data0 to data3 4bytes are written in address addr0. to execute write to other registers initialize nss to high then change to low and re-e nter address then write data. byte 1 byte 2 byte 3 byte 4 byte 5 addr0 addr1 addr2 addr3 dummy data0 data1 data2 data3 0xxx nss mosi miso read addr0 data0 data1 data2 data3 0xxx 0xxx 0xxx 0xxx 0xxx nss mosi miso write picture 3-4 spi command structure 22 ww.3alogics.com confidential | w
TRH031M datasheet www.3alogics.com | in spi communication determining whether it is read or write co mmand depends on first byte of msb. if first byte of msb is 0 then it is write command, and if 1 then it is read command. if msb is bit 7 and lsb is bit 0 then read/write is determined by msb then address is located from bit6~bit1. picture 3-5 is address structure for spi communicat ion. (a) is first address of read command. basically it is addr0 of read command in picture 3-4. as explained above msb value is 1. (b) is address format from addr1 to addr3. msb and lsb are all rfu. (c) is write command address that is write command addr0 in picture 3-4. as explained above msb value is 0. rfu is meaningless value and user can set it at his own dis cretion. 23 confidential picture 3-5 spi address structure
TRH031M datasheet 24 ww.3alogics.com confidential | w chapter4 command 4.1 introduction TRH031M actions are initiated by commands. writing command to a ddress command(0x01) register, TRH031M functions based on current register setting v alue and fifo data value. 4.2 command explanation table 4-1 displays commands available in TRH031M. table 4-1 command register name address reset value command 0x01 0x3f 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 command number name description 5-0 command command register for operating the TRH031M init (3fh) : initializing system after reset. idle (00h): remains in idle mode. (writing 00 to command register will stop actions.) transmit (1ah): transmit fifo data then remains idle. receive (16h): store received data to fifo then remains idle. transceive (1e): transmit fifo data then store received data to fifo. then, idle. init(3fh) command is executed au tomatically when TRH031M is ini tializing system after reset. therefore, this command does not execute by microprocessor. in it(3fh) command automatically stops after set time and b ecomes idle(00h) status. idle(00h) command means idle status. basically TRH031M is not executing any activities. however, this command can activate by microprocessor unlike ini t(3fh). when idle(00h) command is activated by microproc essor, it means discontinuing of any command in action. for
TRH031M datasheet www.3alogics.com | confidential 25 example, when receive(16h) is bei ng executed, writing idle(00h) to command register then TRH031M stops receiving and remains idle mode. transmit(1eh) command encodes fifo stored data and after modula tion, then transmits through tx1 and tx2 pins. when there is no data in fifo, it does not transmit but remains in idle(00h) mode. transmit(1eh) command sends no response comman d for test purpose at times. receive(16h) command is a command to demodulate/decode response signal from antenna then stores in fifo. this command also activates by microproce ssor and used mainly for test purpose. tranceive(1eh) command executes transmit(1ah) and receive(16h) commands continuously. tranceive(1eh) command transmits data in fifo after encoding/mo dulation and stores response signal after demodulation/decodin g. all these actions are perf ormed continuously, and when no response from tags, it remains in receiving mode thus using idl e(00h) command to remain in idle status. activating tranceive(1eh) command when there is no dat a in fifo, all protocols except iso/iec 15693 cannot execute commands, but for iso/iec 15693, a fter transmitting eof signal then receive.
TRH031M datasheet 26 ww.3alogics.com confidential | w 4.3 tr ansmit/receive status check microprocessor checks transmission status by reading TRH031M re gister. not only execution of transmit/receive status but also error occurrence and other sta tus checks are possible. microprocessor occasionally checks information on TRH031M trans mit/receive status and determines next course of action. table 4-2 status1 register name address reset value status1 0x03 0x01 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 modemstate irq err hialert loalert number name description 6-4 modemstate 000: idle - ready status. 001: txsof - transmitting the sof(start of flame). 010: txdata - transmitting data of fifo buffer. 011: txeof - transmitting the eof(end of flame). 100: gotorx - starting receive. 101: preparerx - waiting till selected period in the rxwait register is expired. 110: awaitingrx - waiting for the receiving signal. 111: receiving - receiving the signal. 3 irq displays interrupt occurrence. set interrupt use by utilizi ng ien register. 2 err showing an error state. when errflag register value is 0 th en err value is 0. 1 hialert when fifo stored data si ze is above certain level then value become 1. 0 loalert when fifo stored data si ze is below certain level then value become 1. staus1 register is a register confirming overall transmit/recei ve status. also current executed transmit/receive process can be verified by modemstate of status1 register. one transmit frame is configured by sof(start of frame), data and eof(end of flame ) following iso standard. through modemstate flag of status1 register, can verify which step of frame is bei ng transmitted by transmitter. table 4-2 explains definition of modemstate value. irq flag of status1 (0x03) register obtain high value when inte rrupt occurs by ien (0x06) register setting. when interrupt request completes, it automatically changes to low value. irq flag of status1 (0x03) register perform active high irrelevant of ir qinv value of iconfig (0x2d) register.
TRH031M datasheet www.3alogics.com | confidential 27 err flag of status1 (0x03) register becomes high value when any error occurs from errflag (0x0a) register. this flag as well as irq flag automatically cl ears when errflag (0x0a) register flags are cleared. hialert and loalert flag are registers to check data size in fi fo. for detailed explanations please referred "6.3.3 fifo buffer related functions". table 4-3 status2 register name address reset value status2 0x05 0x00 7-bit 6-bit 5-bit 4-bit 3- bit 2-bit 1-bit 0-bit trunning lockstatus terrflag tadflag rxlastbits number name description 7 trunning when timer is running value is 1. when stopped value is 0. 6-5 lockstatus during operating tag-it protocol, lockstatus of memo ry block save in getblock response. 4 terrflag during operating tag-it protocol, saving errorflag fro m tag response. 3 tadflag during operating tag-it protocol, saving address flag f rom tag response. 2-0 rxlastbits when using iso 14443a protocol, store valid bit quan tity when collision occurs. status2(0x05) register (same as status1(0x03)) is a register to confirm activating status. status2 register displays timer status. trunning flag of status 2 register maintains high value even during timer counting. rxlastbitflag of status2 register indicates number of valid bit s location of last byte received. for example, if conflict occurs in 6th bit after receive command, r xlastbits become 5 and valid bits become 5 bits. every bits of last received byte are received no rmally, rxlastbits becomes 0. please refer to "5.4 anti-collision. lockstatus, terrflag, and tadflag are flags to support ti (texa s instruments) tag-it protocol. in case of tag-it protocol, tag response cannot be divided 8 bits evenly. therefore, TRH031M from tag response stores lockstatus, terrflag, and tadflag data not store by fifo. lockstatus is lock status per specification and te rrflag is error flag. lastly, ta dflag is address flag.
TRH031M datasheet 28 ww.3alogics.com confidential | w 4.4 control control (0x09) register is a register to execute various functi ons. powerdown of control (0x09) register leads TRH031M to stand-by mode using software. during power down mode, TRH031M cannot execute transmit/receiving but power consumption is minimized. (for detailed explanations, please refer to 9.3.2) tstopnow and tstartnow flag are used to execute timer. when writing 1 to tstartnow flag, timer begins counting, and when writing 1 to tstopnow flag, timer counting stops. (for detailed explanations, plea se refer to 10.3) flushfifo function is to delete data remaining in fifo buffer. when tag i s not responding, noise can be a cause. sometimes noise can be recognized as data and stored in fifo. when transmit/receiving wit hout deleting fifo data, incorrect data c aused by noise can be transmitted. therefore, before storing transmitted data to fifo, use flushfifo to delete all fifo data and store data to be transmitted. in powerdown, when set as value 1, the value stays the same. however, flushfifo, tstopnow and tstartnow commands clear to 0 automatically. table 4-4 control register name address reset value control 0x09 0x00 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 powerdown 0 tstopnow tstartnow flushfifo number name description 4 powerdown setting value to 1, internal power consumption is min imized and remains waiting mode. 2 tstopnow setting this value to 1 will initiate timer count. this value automatically changes to 0. 1 tstartnow setting this value to 1 will stop timer. this value automatically changes to 0. 0 flushfifo delete all fifo stored data. this value automaticall y changes to 0.
TRH031M datasheet www.3alogics.com | confidential 29 4.5 error check errflag (0x0a) register is a reg ister to check error during tra nsmit/receiving. if fifo buffer data is full than fifoovfl flag changes to value 1. when fifoovfl occurs, using flushfifo eliminates fifo buffer data and fifoovfl error clears automatically. crcerr displays crc error during transmission, and parityerr displays parity error for iso14443 type a. these two value upda te automatically when transceive command restart. collerr flag sets when collision error occurs. collerr also as parityerr and crcerr automatically updates when command start. (for detailed information on collision, please refer to "5.4 anti-collision", and detailed information on parityerr and crcerr , please refer to"7.2 signal integrity"). table 4-5 errflag register name address reset value errflag 0x0a 0x00 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 fifoovfl crcerr 0 parityerr collerr number name description 4 fifoovfl when fifo data is overflow then value is 1. 3 crcerr when crc check error occurs then value is 1. 1 parityerr when parity check er ror occurs then value is 1. 0 collerr when collision occurs then value is 1.
TRH031M datasheet 30 ww.3alogics.com confidential | w chapter5 protocol 5.1 introduction this chapter explains protocols (iso/iec 14443 a/b, iso15693, t ag-it) and use methods supported by TRH031M. changing protocols are done by changing registers related to protocols. 5.2 tr ansmit data format select to choose a protocol, user must select transmit data format. format implies encoding method and framing method and do not include analog modulation. trh031 m supports total 4 types of protocol and for iso15693, 2 encoding methods are available. th erefore, user can select up to 5 formats. table 5-1 codcontrol register name address reset value codcontrol 0x14 0x01 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 ti_addr txcoding number name description 3 ti_addr used to select address mo de type during tag-it protocol request command. 2-0 txcoding set tx encoding method. 000: set coder to iso 14443 b type mode. 001: set coder to iso 14443 a type mode. 010: set coder to tag-it protocol mode. 110: set coder to iso 15693 standard mode ( 1 out of 256 coding ). 111: set coder to iso 15693 standard mode ( 1 out of 4 coding).
TRH031M datasheet www.3alogics.com | txcoding flag of codcont (0x14) register is a flag to select transmit d ata format. below table is transmitting data format based on txcoding value. ti_addr flag is used to store address flag value to be transmitted from tag-it protocol. table 5-2 transmit data format by tx c od i ng value txcoding standard format 000 iso 14443b nrz 001 iso 14443a modified miller 010 tag-it pulse width modulation 110 iso 15693 (1 out of 256 coding) pulse position modulation 111 iso 15693 (1out of 4 coding) p ulse position modulation confidential 31 picture 5-1 encoding method by protocol
TRH031M datasheet 32 ww.3alogics.com confidential | w picture 5-1 displays encoding method by protocol. iso 14443a ty pe (picture 5-1(a)) encode by modified miller form and two data formats to display 0. iso 144 43b type (picture 5-1(b)) is the most standard encoding method, nrz coding. iso 15693 two forms of ppm (pulse position modulation) method to indicate data. picture 5-1(c) and picture 5-1(d) display two encoding method for iso 15693. ppm format is a method of data value to t abularize as pulse location. reader can select either one of these two formats, and tag responds by both data format. tag-it protocol use pwm (pulse width mo dulation) method. pwm method di stinguishes data by pulse length. 5.3 re ceiver data format select receiver data format is determined by registers same as transmi t data. rxframing flag of decodcontrol(0x1a) register performs this activity. table 5-3 d isplays receiver data format by rxframing value. table 5-3 decodcontrol register name address reset value decodcontrol 0x1a 0x08 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 zrafcoll rxframing 0 0 number name description 5 zrafcoll store received data after collision as 0. 4-2 rxframing 000: set decoder to tag-it protocol mode. 01x: set decoder to iso 14443 a type mode. 10x: set decoder to iso 15693 mode. 11x: set decoder to iso 14443 b type mode. picture 5-2 displays receiver data format by protocol. all prot ocols use sub-carrier, and they use manchester coding method excep t iso 14443b type. iso 14443a typ e and iso 14443b type use 847 khz subcarrier, and iso 14443b type use bpsk modulation. bp sk modulation is a method changing phase 180 when data is changed. iso 15693 use same format with iso 14443a type, and subcarrier speed is half of iso 14443a, 423 khz. for tag-it , change subcarrier speed to tabularize data. for data 1, subcarrier changes from 484 khz to 433 khz, and for data 0, changes from 423 khz to 484 khz conversely.
TRH031M datasheet www.3alogics.com | zrafcoll flag of decodcontrol(0x1a) register used only by iso 14443a typ e. when zrafcoll flag is set to 1, after collision error received data is saved in fifo as 0. this function simplifies use of iso14443a anti-collision. (a) 14443a (b) 14443b (c) 15693 (c) tag-it data 1 data 0 data 1 data 0 data 1 data 0 data 1 data 0 picture 5-2 receiver data format by protocol 33 confidential
TRH031M datasheet 34 ww.3alogics.com confidential | w 5.3.1 receive de lay time rxwait(0x21) register is a register to set the delay time betwe en begin receiving after transmit ends. using rxwait(0x21) can block noise after transmit. howeve r, if delay time is set too long than may not able to receive response from tag thus set the pro per value through testing. delay time is a value rxwait multiplied by 128/fc. table 5-4 rxwait register name address reset value rxwait 0x21 0x06 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit rxwait number name description 5-0 rxwait setting the interval time after transmission before rece iving. 5.3.2 bit level re ceiving collision occurrence from tag du ring data receiving or if less than 1 byte data is received, to display the number of normal received bits from last received b ytes, rxlastbits of status2 register is used. rxlastbits are in 3 bits, and value are 0 when all bytes are received norm ally.
TRH031M datasheet www.3alogics.com | 5.4 anti-colli sion if multiple tags are in rf field, all tags respond at same time , and tag signals are mixed in rf field making it difficult to distinguish data. therefore, reade r must read tags in rf field sequentially. in order to avoid tag collision, anti-collision a lgorithm is used. for iso 14443b and iso 15693 tag collision detection is required for anti-collisio n to function. however, iso 14443a requires hardware detection of collision location and collision occurrence to activate anti-collision function. TRH031M has ability to detect collision and its locat ion when collision occurs. picture 5-3 collision detection 5.4.1 collision detection picture 5-3 displays how TRH031M detects collision. tag a and t ag b have different value from 4 th bit. when tag a and tag b have different value (as seen on pict ure 5-3), receiver cannot determine whether received data is 0 or 1. when TRH031M receive s a signal undetermined whether 0 or 1 (seen as picture 6-3), location is stored at collpos flag of collpos(0x0b) register and set to 1 on collerr flag of errflag(0x0a) register thus microprocessor can accomplish anti- collision functions. parit y bit is excluded from collpos calculation. 35 confidential
TRH031M datasheet table 5-5 collpos register name address reset value collpos 0x0b 0x00 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit collpos number name description 7-0 collpos indicate a position where first collision occurred. when collision is detected zrafcoll is set and all data after first collision are stored in fifo as 0. this type of data processing is very convenient to develop soft ware to handle anti-collision meeting iso standard. picture 5-4 register value during collision occurrence 36 ww.3alogics.com confidential | w above picture 5-4 displays an example of two tags collision. pi cture 5-4(a) is uid of two tags. first byte has same value of 74 but from second byte each value of 5b and 07 are given. picture 5-4 (b) is tabularized uid in binary numbers. picture 5-4(c) di splays actual receiving steps. for iso 14443a, lsb is received first and steps as picture 5-4(c) occur s. when TRH031M terminates receiving, collision occurs in 11 th receiver bit, therefore, collpos flag value becomes b and rxlastbits value becomes 0.
TRH031M datasheet www.3alogics.com | if zrafcoll is set as 1, 2 nd byte is stored to fifo as 03h and lower level 3 bytes are store d as 00h. if zrafcoll is set to 0, data value after collision becomes unpredictable v alue different from original uid. 5.5 bit leve l data transmit/receive table 5-6 bitframe register name address reset value bitframe 0x0f 0x00 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit rxalign tmaskflag txlastbits number name description 6-0 rxalign align bit for received data. 3 tmaskflag used for tag-it protoc ol. from sid request command it is used when using mask bit and mask length value is stored in txlastbits, t hen, selected mask value from data stored in fifo and transmitted to tag- it tag. 2-0 txlastbits use when transmitting less than a byte. txlastbits is a bit value for data to be transmitted. TRH031M can transmit/receive data by bit level. for bit level t ransmit, txlastbits flag of bitframe(0x0f) register is used and for bit level receiving rxalign flag is used. picture 5-5 bit level transmit 37 confidential
TRH031M datasheet above picture 5-5 displays bit level transmit. if fifo stored d ata is same as picture 5-5(a), data is tabularized in binary numbers as seen in picture 5-5(b). if txlastbits is set to 3 and transmit command carries out, then first byte 74 is all transmitted and second data 03 is transmitted up to 3 bits. picture 5-6 bit level receive 38 ww.3alogics.com confidential | w picture 5-6 displays bit level receiver steps. when receiver da ta (on picture 5-6(a)) rxalign value is set to 3, data is stored in fifo as picture 5-6 (b) be ginning 4 th bit. picture 5-6(c) displays hexadecimal data stored in fifo.
TRH031M datasheet www.3alogics.com | confidential 39 5.6 protocol this section describes each prot ocol and related register funct ions. 5.6.1 iso/iec 14443a proto col setting decoding method decoding function improvement setting is possible with iso 1444 3a type. 3alogics highly recommends this function since there are many advantages with v irtually no disadvantage. to use this function, adcdmd flag of rxcontrol2(0x1e) register must be set to 1. table 5-7 rxcontrol2 register name address reset value rxcontrol2 0x1e 0x01 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit adcdmd 0 0 0 0 0 dcdsrc 1 number name description 7 adcdmd set iso 14443a decoding method. 1 dcdsrc use to define input signal of receiver decoder logic. 0: use response signal from card as input. 1: use signal through testin pin as input. dcdsrc flag of rxcontrol2(0x1e) register is a flag to determine which signal to decode. when dcdscr is 0, signal from receiver is decoded and when it is 1, signal from testin pin is decoded. signal received from testin pin is decoding function testing pu rpose and typically is set to 0 when used for transmit/receive purpose.
TRH031M datasheet modulation width changes iso 14443a type protocol communication from reader to tag utili ze 100% ask modulation ? modified miller coding method. modified miller tabularize data value by pulse location, and thr031m allows functionality to adjust pulse width. modwidth flag of modwidth(0x15)register is used for 14443a type pulse widt h adjustment in transmit sign al. modwidth unit is 128/fc. table 5-8 modwidth register address reset value name 0x15 0x10 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit modwidth 0 0 modwidth number name description 5-0 modwidth set 100% modulation width for iso14443a. t mod = 2(modwidth+1)f c 40 ww.3alogics.com confidential | w picture 5-7 modulation width
TRH031M datasheet www.3alogics.com | confidential 41 5.6.2 iso/iec 14443b protocol iso/iec 14443b type frame setting TRH031M contains functionality for frame adjustment using 14443 b type protocol. using iso 1444b type, from frame sof, eof and egt length are predetermine d. through bframing (0x17) register user can adjust values within specification. table 5-9 bframing register name address reset value bframing 0x17 0x00 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 eofwidth charspacing sofwidth number name description 5 eofwidth 0: set the eof to length of 10 etu. 1: set the eof to length of 11 etu. 4-2 charspacing set egt width. set in 128 x fc multiples. 1-0 sofwidth 00: set the sof to length of 10 etu low 2 etu high. 01: set the sof to length o f 10 etu low 3 etu high. 10: set the sof to length o f 11 etu low 2 etu high. 11: set the sof to length o f 11 etu low 3 etu high.
TRH031M datasheet picture 5-8 displays sof and eof used in iso 14443b type. picture 5-8(a) is frame architecture of iso 14443b type. frame begins with sof and ends with eof, and characters are located in between. picture 5-8(b) displays form of sof. sof is a signal with low section length is 10~11etu and high section length is 2~3etu. this value can be adjusted through sofwidth flag. picture 5-8(c) displays eof signal. eof length is10~11etu and can be adjusted using eofwidth flag. picture 5-8 sof and eof length picture 5-9 egt length picture 5-9 explains egt(extra guard time). same as picture 5-8 , character comprise of start bit and stop bit with total of 8 binary data. delay time between tw o characters is called egt. from specification egt value is 0~57us when transmitting and 0~19us when receiving. user can adjust egt length by 128/fc using charspacing flag of bframing(0x17) register. 42 ww.3alogics.com confidential | w
TRH031M datasheet www.3alogics.com | confidential 43 chapter6 fifo buffer 6.1 introduction TRH031M has 64-byte fifo buffer. this fifo buffer stores data temporarily while data transfer between microprocessor and trh 031m. when microprocessor sends r eceive command, data is written to fifo buffer, and if transmit command is sent then re ceived data is stored in fifo. fifo related functions, same as other TRH031M functions, are execute d through register. 6.2 fifo buffer data input/output fifo buffer input/output is acco mplished using fifodata(0x02) r egister. microprocessor write to fifodata(0x02) register the data to be transmitted and read dat a received through fifodata(0x02) register. fifodata(0x02) register outputs first data stored in fifo. again, fifodata(0x02) register read data sequentially based on first i n first out basis. table 6-1 fifodata register name address reset value fifodata 0x02 0xxx 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit fifodata number name description 7-0 fifodata fifo buffer input/output register fifolength flag of fifolength(0x04) registe r is a register expressing fifo buffer stored data in byte level. fifolength flag comprises of 7 bits t o express up to 64 bytes.
TRH031M datasheet 44 ww.3alogics.com confidential | w table 6-2 fifolength register name address reset value fifolength 0x04 0x00 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 fifolength number name description 6-0 fifolength show the number of bytes stored in the fifo buffer. 6.3 fifo buffer related functions 6.3.1 fifo buffer data deletion fifo buffer data can be deleted by flushfifo flag of control(0x09) register. finally fifolength(0x04) becomes 0 and fifo can store up to 64 bytes. flushfifo command allows inaccurate data deletion due to noise before transmit/receive f unction. 6.3.2 fifo buffer error when data is full in fifo buffer, error occurs and sets fifoovfl of errflag(0x0a)register to 1. fifoovfl error can be cleared using flushfifo command. 6.3.3 fifo buffer caused interrupt there can be interrupts due to TRH031M fifo buffer stored data quantity, and these interrupts occurs by waterlevel flag of fifolevel(0x29) register value.
TRH031M datasheet www.3alogics.com | table 6-3 fifolevel register address reset value name 0x29 0x08 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit fifolevel 0 0 waterlevel number name description 5-0 waterlevel set hialert and loalert alert level. hialert occurs when fifo availabl e space is below waterlevel. loalert occurs when fifo stored data quantity is below waterlevel. confidential 45 byte 64 byte 63 byte 62 byte 61 byte 60 byte 59 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 loalert threshold hialert threshold loalert interrupt request no interrupt request hialert interrupt request waterlevel = 4 picture 6-1 waterlevel value interrupts picture 6-1 displays fifo buffer stored data quantity and inter rupt occurrence due to waterlevel value. total of 64 bytes can be stored in fifo. loalert interrupt occurs when fifo data is less than waterlevel specified value and hialert interrupt occurs when less space is available in fifo then waterlevel specified value. other occasions, interrupt do not occur.
TRH031M datasheet 46 ww.3alogics.com confidential | w chapter7 signal integrity 7.1 introduction wireless communication has number of insecure elements. electro magnetic waves from other peripherals, natural environment changes and other elements imp act communication error. therefore, all protocols contain methods to detect error, and t rh031m provides error correction methods by hardware. 7.2 signal integrity setting method table 7-1 signal integrity check method by protocol and its reg ister setting method protocol type redundancy check method crcb flag parityodd flag parityen flag iso 14443a 16-bit crc (iso 14443a), odd parity 0 1 1 iso 14443b 16-bit crc (iso/iec3309) 1 0 0 iso 15693 16-bit crc (iso/iec3309) 1 0 0 tag-it 16-bit crc (iso/iec3309) 1 0 0 table 7-1 tabularizes signal integrity checking method by proto col and its register setting methods. crcb flag of register redundancy(0x22) is a flag to activate crc met hod. parityen is a flag to determine parity check use. parityodd flag determines to use odd parity or even parity. as seen on above table, all protoco ls except iso 14443a type do no t use parity error check method and also crc type use different format for iso 14443a type.
TRH031M datasheet www.3alogics.com | confidential 47 table 7-2 redundancy register name address reset value redundancy 0x22 0x03 7-bit 6-bit 5-bit 4- bit 3-bit 2-bit 1-bit 0-bit 0 crcwr crcb 0 rxcrcen txcrcen parityodd parityen number name description 6 crcwr store received crc value on fifo. 5 crcb setting crc calculation type. 0: iso 14443a type 1: iso/iec3309 (iso14443b type and iso 15693) 3 rxcrcen processing crc calculation for received data. 2 txcrcen adding crc calculation for transmission data. 1 parityodd setting parity calculation. 14443 a-type only. 0: even parity 1: odd parity 0 parityen setting parity error detecting code. 14443 a-type only . crcwr flag of redundancy(0x22) register writes received crc value to fifo buffer. when crcwr is set to 1, microprocessor reads crc value from fifo and calcu lates crc value in software level to confirm signal integrity. rxcrcen and txcrcen are flags to determine to use crc during transmit/receive. when txcrcen is set to 1, crc is sent with transmit data, and when rxcrcen is set to 1 then data is received and calculates crc for signal integrity. iso 14443a ma y not use crc based on command type, thus, user should confirm crc use and may need to set rxcrcen and txcrcen . table 7-3 crcpresetlsb register name address reset value crcpresetlsb 0x23 0x63 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit crcpresetlsb number name description 7-0 crcpresetlsb store crc preset value lsb 8bit.
TRH031M datasheet 48 ww.3alogics.com confidential | w table 7-4 crcpresetmsb register name address reset value crcpresetmsb 0x24 0x63 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit crcpresetmsb number name description 7-0 crcpresetmsb store crc preset value msb 8bit. crcpresetlsb(0x23) and crcpresetmsb(0x24) register are register s determining initial value of crc calculation. crc preset value are 8 bits each through 2 reg isters since 16-bit crc is used. this register can change by micr oprocessor. therefore, user can set crc operation initial value. table 7-5 crcresultlsb register name address reset value crcresultlsb 0x0d 0xxx 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit crcresultlsb number name description 7-0 crcresultlsb store crc calculation result lsb 8bit. table 7-6 crcresultmsb register name address reset value crcpresetmsb 0x0e 0xxx 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit crcresultmsb number name description 7-0 crcresultmsb store crc calculation result msb 8bit. crcresultlsb(0x0d) and crcresultmsb(0x0e) register are registers to store crc calculation result. crcerr flag of errflag(0x0a) register can be confirmed by microprocess or. also microprocessor uses crcresultlsb and crcresultmsb to confirm error occurrence.
TRH031M datasheet www.3alogics.com | confidential 49 chapter8 interrupt 8.1 introduction TRH031M supports various types of interrupt. using interrupt be nefits for microprocessor to control TRH031M. first, processing speed enhancement can be exp ected and second, efficiency in microprocessor calculation. if microprocessor controls more than 2 devices, benefits of interrupt enhance. TRH031M supports total of 6 interrupts and user can se lect choose to use any interrupt. 8.2 interrupt use method table 8-1 ien register name address reset value ien 0x06 0x00 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit setien 0 timerien txien rxien idleien hialertien loalertien number name description 7 setien 0: clear bit. from 0~6, set marked bit as 0. 1: set bit. 0~6 set marked bit as 1. 5 timerien 0: not transfer timerirq interrupt signal to irq pin 1: transfer timerirq interrupt signal to irq pin. 4 txien 0: not transfer txirq interrupt signal to irq pin. 1: transfer txirq interrupt signal to irq pin. 3 rxien 0: not transfer rxirq interrupt signal to irq pin. 1: transfer rxirq interrupt signal to irq pin. 2 idleien 0: not transfer idleir q interrupt signal to irq pin. 1: transfer idleirq interrupt signal to irq pin. 1 hialertien 0: not transfer hialertirq signal to irq pin. 1: transfer hialertirq signal to irq pin. 0 loalertien 0: not transfer loalertirq interrupt signal to irq p in. 1: transfer loalertirq interrupt signal to irq pin.
TRH031M datasheet 50 ww.3alogics.com confidential | w TRH031M alerts microprocessor through irq pin when interrupt oc curs in ien(0x06) register setting. therefore, use r must select interru pts to be used set in ien(0x06) register. microprocessor through irq pin is alerted of interrupt occurren ce but to know which interrupt must confirm by reading from irq(0x07) register. when microproc essor set the interrupt in ien(0x06) and verify interrupt occurrence through irq pin, micr oprocessor read irq(0x07)register. irq(0x07)register is automatically set to 1 when interrupt occu rs but maintains the value until microprocessor change the value to 0. when multiple interrupt o ccur, if not microprocessor initialize interrupt to 0, despite additional interrupt occurre nce irq pin has no impact thus microprocessor is not aware of interrupt occurrence. therefore, interrupt request is recommended to re-initialize after occurrence . occurred interrupt request i s modified in irq(0x07)register and other values to be maintained as previous value, ien(0x06)regis ter and irq(0x07)register have different read/write method s than other registers. ien(0x06) and irq(0x07) registers are changeable by bit level. basically user can change specific bit value and keep others as is. this function is use ful when initializing single interrupt. table 8-2 irq register name address reset value irq 0x07 0x00 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit setirq 0 timerirq txirq rxirq idleirq hialertirq loalertirq number name description 7 setirq 0: clear bit. from 0~6, set marked bit as 0. 1: set bit. 0~6 set marked bit as 1. 5 timerirq 0: timervalue register is not 0. 1: timervalue register is 0. 4 txirq 0: fifo data not transmitted. 1: fifo data transmitted. 3 rxirq 0: receiving not complete. 1: receiving complete. 2 idleirq 0: not in idle mode. 1: command execution complete and remains in idle mode. 1 hialertirq 0: fifo available space is more than waterlevel. 1: fifo available space is less than waterlevel. 0 loalertirq 0: fifo data is more than waterlevel. 1: fifo data is less than waterlevel.
TRH031M datasheet www.3alogics.com | picture 8-1 ien and irq register setting method above picture 8-1 displays ien(0 x06) register and irq(0x07) reg ister setting method. picture 8- 1(a) displays register setting of bit value 1, and picture 8-1( b) displays register bit setting of 0. from picture 8-1 (a) and (b) if first byte data is previous data before written, 2 nd byte is ien(0x06) or irq(0x07) written data. lastly 3 rd byte changed value after it is written. as seen on picture 8-1, when setting ien(0x6) or irq(0x0 7)register as either 1 or 0 is determined by msb then only bit 1 is changed and other bits maintains previous value. table 8-3 irqconfig register address reset value name 0x2d 0x02 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit irqconfig 0 0 0 0 0 0 irqinv 0 number name description 1 irqinv set polarity of irq pin. 0: active high (1 when interrupt occurs) 1: active low (0 when interrupt occurs) irqconfig(0x2d) register is a register to set polarity of inter rupt. when irqinv is set to 1, irq pin maintains the value 1 during idle and changes to 0 when int errupt occurs. when irqinv is set to 0, conversely irq pin maintains 0 value during idle mode and changes to 1 during interrupt occurrence. confidential 51
TRH031M datasheet 52 ww.3alogics.com confidential | w chapter9 power management 9.1 introduction TRH031M provide power down mode to minimize power consumption. user can minimize power consumption during reader chip idle mode using power down mode. 9.2 power down mode effect when power down mode is executed, TRH031M stops all devices con suming power and maintain idle until wake-up. bel ow table displays pin status du ring power down mode. for optimum performance of power down mode entry pin must assign di fferent value other than high-z. . table 9-1 pin assignment in power down mode symbol i/o description xin i oscillator disabled irq o output high tx1 o output low tx2 o output low csb, wrb, rdb i input data7 C data0 i input pale,testin i input addr2, addr1, addr0 i input testout, test2o o output low rx i input vmid i input xout o oscillator disabled rst i input (high)
TRH031M datasheet www.3alogics.com | confidential 53 9.3 powerdown mode directions 9.3.1 hardware powerdown mode hardware power down mode is a method to minimize power consumpt ion using TRH031M rst pin. TRH031M activates power down mode when rst pin is 1. dur ing power down mode, TRH031M internal main clock does not oscillate and needs some t ime after rst is given low value and to re-activate. its because stopped oscillation to resume clock and to stabilize requires a certain time. this required time is less than 500us. 9.3.2 software powerdown mode software power down mode activates when control(0x09) register sets as powerdown flag to 1, and during software power down mode, all internal current co nsumption is minimized. this process is actually the same as hardware power down mode. in s oftware power down mode, host interface remains in action mode to release from power dow n mode. same as hardware power down mode, in software power down mode clock does not osc illate.
TRH031M datasheet chapter10 timer 10.1 introduction microprocessor executes various t imer operations. using timer related registers, timer speed, timer control by event and timer interrupt occurrence are possi ble. 10.2 timer setting timer speed is determined by tprescaler flag value of timerclk(0x2a) register. timer speed implies changes in speed of timer actual value. tprescaler is divided into total of 5 bits. timer speed is determined by 13.56mhz cycle. in below equation, t timerclock implies timer speed. 54 ww.3alogics.com confidential | w 13.56mhz 2 7.73 2 prescaler t pr == ns t escalert timerclock tprescaler value can be set from 0 to 21, therefore, possible t timerclock value is from 74ns to 150ms. table 10-1 timerclk register address reset value name 0x2a 0x07 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit timerclk 0 0 trestart tprescaler number name description 5 trestart if this value is 1, timer count is completed to 0 then reload treloadvalue to automatically restart timer. 4-0 tprescalar set timer count speed.
TRH031M datasheet www.3alogics.com | from timerclk(0x2a) register, trestart is a register to auto re-st art timer automatically. if trestart is already set, do not reduce the timer value to 0, and when t imer value is 1, treloadvalue value is reloaded and begins re-counting. TRH031M timer begins counting from designated value. user can s et timer start value using treloadvalue flag of treloadvalue(0x2c) register. table 10-2 treloadvalue register address reset value name 0x2c 0x0a 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit treloadvalue treloadvalue number name description 7-0 treloadvalue the timer loads this value, when it works. from timer start event to timer to have specific timer value, c an be obtained using below equation. treloadvalue implies timer start value, and timervalue is current timer value. ) re( timervalue loadvalue t tt timerclock timer = ? subsequently, t timer value is estimated from 74ns to 40s. table 10-3 timervalue register address reset value name 0x0c 0x05 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit timervalue timervalue number name description 7-0 timervalue show the current value of the timer. confidential 55 timervalue flag of timervalue is a register to display current timer value . timervalue flag comprises of 8 bits. timervalue is made of total 8 bits thus timer can count from 0 to 2 64 .
TRH031M datasheet 56 ww.3alogics.com confidential | w 10.3 timer function basically timer can start or stop using tstartnow and tstopnow flag of control(0x09) register. setting tstartnow to 1, timer load treloadvalue value to timervalue flag and begin counting as reducing timervalue value by 1. when timer is counting, user sets tstartnow to 1. then, timer stops and displays consumed time through timervalue value. other than timer function through control(0x09) register to uti lize timer for transmit/receive select tcontrol (0x2b) register. tcontrol(0x2b) register contro ls timer count, and it is used when transmit/receive begin or end. for example, if user wants to know the amount of time after transmit complete, tstarttxend of tcontrol(0x2b) register set to 1. table 10-4 tcontrol register name address reset value tcontrol 0x2b 0x06 7- bit 6- bit 5- bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 tstoprxend tstoprxbe tstarttxend tstarttxbe number name description 3 tstoprxend when finished data receiving, timer end. 2 tstoprxbe when starting data receiving, timer start. 1 tstarttxend when finished data sending, timer end. 0 tstarttxbe when starting data sending, timer start. tstoprxend is a flag to stop timer after transmit completion, and tstoprxbe is a flag to start timer when receiver begins. trunning flag of secondarystatus register displays current timer status. when start event begins, timer begins to count and trunning flag becomes 1. also when end event begins, timer stops counting and trunning flag returns to 0. timer is set to create interrupt. timerlrq flag of irq register is an interrupt request when timer value becomes 0.
TRH031M datasheet www.3alogics.com | chapter11 analog 11.1 transmitter analog transmitter comprise of control block, ask modulator and driver. transmitter transmits modulated 13.56mhz carrier frequency simultaneously controls tx 1 and tx2 pin output signals. 11.2 transmitter structure picture 11-1 transmitter structure picture 11-1 displays transmitter configuration. TRH031M use t wo transmitter drivers for antenna signal efficiency. 11.3 transmitter function transmitter setting can be divided into signal type selection and output power selection. next chapter explains transmitter setting method. confidential 57
TRH031M datasheet 58 ww.3alogics.com confidential | w 11.3.1 tx1 and tx2 function setting transmitter transmit tx_i (transferred digital signal for modul ation) modulated 13.56mhz carrier signal through tx1 and tx2. also output signal from tx1 and tx2 for filtering and matching activate antenna through few external elements. tx1 and tx2 out put signal can be set in various format through txcontrol(0x11) register. table 11-1 txcontrol register name address reset value txcontrol 0x11 0x58 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 modulatorsource f100ask tx2inv tx2cw tx2rfen tx1rfen number name description 6-5 modulatorsource select the modulator source 00: constant low 01: constant high 10: internal coder source 11: testin pin source 4 f100ask 0: ask modulation depth is determined by modconductance value. 1: fix ask modulation depth to 100%. 3 tx2inv 0: tx2 pin and tx1 pin output carrier signals are inphas e. 1: tx2 pin output carrier signal is 180? phase to tx1. 2 tx2cw 0: tx2 pin and tx1 pin output signals are modulated. 1: tx2 pin output signal is not modulated. 1 tx2rfen 0: tx2 pin not used. (output constant low value) 1: tx2 pin used. (output rf signal) 0 tx1rfen 0: tx1 pin not used. (output constant low value) 1: tx1 pin used. (output rf signal) table 11-2 tx1 related settings tx1rfen f100ask tx_i signal on tx1 0 x x low 1 0 0 13.56mhz carrier f requency modulated 1 13.56mhz carrier frequency 1 1 0 low 1 13.56mhz energy carrier
TRH031M datasheet www.3alogics.com | confidential 59 table 11-2 displays tx1rfen and f100ask flag of txcontrol(0x11) register and tx1 output signal by tx_i (transferred digital signal for modulation). tx1rfen flag of txcontrol(0x11) register is a flag for tx1 operation. until tx1rfen is set to 1, there is no output signal from tx1. when tx1rfen set to 1, transmitter modulates tx_i (transferred digital signa l for modulation) based on f100ask value. when f100ask is set to 1, 100% ask modulation occurs and when f100ask is set to 0, user can modify modulation index based on modconductance value. (6 ~50% ask) table 11-3 tx2 related settings tx2rfen f100ask tx2cw tx2inv tx_i signal on tx2 0 x x x x low 1 0 0 1 0 13.56mhz carrier frequency modulated 1 13.56mhz carrier frequency 0 0 13.56mhz carrier frequency modulated, 180?phase shift relative to tx1 1 13.56mhz carrier frequency, 180?phase shift relative to tx1 1 1 x 13.56mhz carrier frequency 0 x 13.56mhz carrier frequency, 180?phase shift relative to tx1 1 0 0 0 low 1 13.56mhz carrier frequency 1 0 high 1 13.56mhz carrier frequency, 180?phase shift relative to tx1 1 0 x 13.56mhz carrier frequency 1 x 13.56mhz carrier frequency, 180?phase shift relative to tx1 table 11-3 displays flag value of txcontrol(0x11) register and tx2 output signal by tx_i (transferred digital signal for modulation). tx2 as well as tx1 output signal only when tx2rfen is set to 1 and select modulation method by f100ask value. however, tx2 has two additional setting compared to tx1. tx2cw regardless of tx_i (transferred digital signal for modulation) signal to tx2 is a flag to output as same as when tx_i value is 1. lastly, tx2inv is a flag to output tx1 and tx2 phas e in 180 reverse.
TRH031M datasheet 60 ww.3alogics.com confidential | w 11.3.2 tx1 and tx2 output power setting tx1 and tx2 output drivability ch ange by conductance value. as conductance value rise, tx1 and tx2 output rise as well. tx1 and tx2 driver conductance use cwconductance of cwconductance(0x12) register and can be adjusted. (r p : p-channel resistance) table 11-4 cwconductance register name address reset value cwconductance 0x12 0x3f 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 cwconductance number name description 5-0 cwconductance this register value defines the output driver con ductance of pins tx1 and tx2. table 11-5 tx1 and tx2 p-channel resistance cwconductance r p [ohm] 0 1 10.14 2 6.33 4 4.60 8 2.98 16 2.11 32 1.63 table 12-3 is a table to display tx1 and tx2 p- channel resistance. p-channel resistance is inverse to driver conductance. if cwconductance value is set to 3, p-channel resist ance value becomes 3.9 with parallel calculated considering when cwconductance 1 value is 10.14 and when cwconductance 2 value is 6.33.
TRH031M datasheet www.3alogics.com | confidential 61 11.3.3 tx1 and tx2 modulation index adjustment if f100ask is not set to 1, tx1 and tx2 modulation index is impacted by modconductance of modconductance (0x13) register value. the role of modconductance is to adjust driver conductance when tx1 and tx2 process modulation and impacts ask modulation index changes. (r p : p-channel re sistance) table 11-6 modconductance register name address reset value modconductance 0x13 0x07 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 modconductance number name description 5-0 modconductance determine modulation conductance value between t x1 pin and tx2 pin. table 11-7 tx1 and tx2 modulation p-channel resistance modconductance r p [ohm] 0 1 12.60 2 10.14 4 8.47 8 7.25 16 6.33 32 5.07 table 11-7 is a table displaying tx1 and tx2 modulation p-channel resistance. same as cwconductance , when two or more bits are set modconducatance also result in adding each rp value in parallel. changes in rp change modulation index but it is impacted by rp value and matching circuit simultaneously, therefore, there can be minor changes based on matching methods. changes in modulation index due to modconducatance value change, please refer to "trh03xm cookbook". 11.3.4 recognition distance and power consumption recognition distance and power consumption have proportional re lationship. as transmitter power consumption increase recognition distance also increases. therefore, there is a trade-off between recognition distance and power consumption. user should consider this fact when designing.
TRH031M datasheet 11.4 receiver receiver execute converting 13.56mhz tag signal through rx pin and sensing envelop to convert to digital signal. this process is called demodulation. 11.5 receiver structure 62 ww.3alogics.com confidential | w decoder voltage reference power management envelop detector filter vga comparator buffer offset correction rxcontrol1<1:0> rxthreshold<2:0> rx rxcontrol1<2> vmid rx_i pwdown rx_enable mux picture 11-2 receiver structure receiver configuration is displ ayed in picture 11-2. receiver performs demodulation process through envelop detector, vga and comparator. vmid informs to comparator signal distinction standard level.
TRH031M datasheet www.3alogics.com | confidential 63 11.6 receiver functions receiving process can be divided into various levels. next sections will describe each role and possible settings. 11.6.1 envelope detector envelop detection is a level to delete carrier from received si gnal and output envelop changes. TRH031M suggest pmos diode structure for more stable data recei ving. 11.6.2 offset collection in this level, offset collection for more clear and ideal dc bi asing. to find this dc bias point, standard methods such as pass filtering and ac coupling were us ed. 11.6.3 variable gain amplifier: vga demodulated signals are amplified for improved performance. vga gain can be controlled using vgagain flag of rxcontrol1(0x19) register. table 11-9 displays vga gain based on vgagain flag value. table 11-8 rxcontrol1 register name address reset value rxcontrol1 0x19 0x02 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 vgagain number name description 2-0 vgagain adjust rx amp gain. this value can be changed by protocol type and working environm ent.
TRH031M datasheet table 11-9 gain value by vga gain setting vgagain gain [db] (simulation results) 0 6.02 1 12.04 2 15.56 3 18.06 4 20.00 5 21.58 11.6.4 comparator comparator is a last step to convert output signal through enve lop detector and vga to digital signal. if comparator (as seen on picture 11-3 (a)) transforms very fast at certain threshold point, inaccurate signals will output in noise environment. in this ty pe of situation, comparator transformation characteristics should be modified. thus, trh031 m allows hysteresis range (picture 12-3(b)) in comparator. hysteresis range can be modified by hyr of rxthreshold(0x1c) register. table 11-10 rxthreshold register address reset value name 0x1c 0x10 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit rxthreshold 0 cro hyr crv number name description 6 cro set comparator reference on or off. (comparator reference o n) 5-3 hyr set comparator hysteresis range. 2-0 crv set comparator reference voltage. picture 11-3 (a) ordinary comparator noise impact (b) hysteresi s added comparator noise impact 64 ww.3alogics.com confidential | w
TRH031M datasheet www.3alogics.com | confidential 65 table 11-11 hysteresis range of comparator based on hyr value hyr(hysteresis range) hysteresis ranges/v trp [mv] (simulation results) 0 34 1 53 2 72 3 90 4 108 5 128 table 11-11 displays hysteresis range based on hyr flag value. as seen on above table, hysteresis range of comparator can be modified from 34mv to 128 mv. also comparator can set input reference voltage. input reference voltage is standard vo ltage that comparator can determine whether 0 or 1. to adjust comparator input reference voltage value, cro flag must be set to 1. if cro is set to 1, input reference voltage value changes by crv value of rxthreshold(0x1c) register. if cro value is set to 0, input referen ce voltage is 1.65v irrelevant of crv value. table 11-12 displays inpu t reference voltage value by crv value. table 11-12 comparator input ref erence voltage by crv value crv (comparator reference voltage) reference voltage [v] (simulation results) 0 1.743 1 1.713 2 1.681 3 1.621 4 1.591 5 1.560
TRH031M datasheet chapter12 test 12.1 introduction TRH031M supports debugging process after design completion usin g various test features. using testout pin for signal output fr om TRH031M, user can test functionality. 12.2 how to use test pin picture 12-1 is transmit and receiving process. picture 12-1 observable signals using test pin 66 ww.3alogics.com confidential | w
TRH031M datasheet www.3alogics.com | confidential 67 table 12-1 testoutsel register name address reset value testoutsel 0x26 0x00 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 testsel number name description 2-0 testsel select send out signal to testout pin. 000: constant low 001: constant high 010: demodulated rx signal 100: not modulated tx signal picture 13-1 displays transmit/r eceive process. picture 12-1(a) is actual signal on antenna. picture 12-1(b) is transmitted digital signal from digital block to ana log block for alteration. picture 12- 1(c) is digital signal originally received from tag and demodul ated from analog block and sent to digital block. user can confirm activation using testout pin to observe picture 12-1(b) and picture 12-1(c) signal. testout pin output can be set using te s t s e l flag of testoutsel(0x00) and if the value is 4, then picture 12-1(b) and value is 2 then pic ture 12-1(c) signal output occur.
TRH031M datasheet 68 ww.3alogics.com confidential | w chapter13 electrical characteristics 13.1 operating condition range symbol parameter min typ max unit t op operating temperature range -25 +25 +85 dvdd digital power supply 3.0 3.3 3.6 v avdd analog power supply 3.0 3.3 3.6 v tvdd transmitter power supply 3.0 3.3 3.6 v 13.2 current consumption symbol parameter conditions min typ max unit i dvdd digital supply current idle command 3.9 4.7 5.6 ma power down mode 0.13 0.16 0.22 ua i avdd analog supply current receiver on 2.15 2.26 2.35 ma power down mode 0.047 0.056 0.068 ua i tvdd transmitter supply current continuous wave antenna unconnected 80 100 120 ma tx1 and tx2 unconnected, tx1,2 disable / clock on 7 8 10 ua tx1 and tx2 unconnected, tx1,2 disable / clock off 0.01 0.011 0.013 ua lek total leakage current power down mode 0.19 0.23 0.3 ua i op total operating current operating mode 86 107 128 ma
TRH031M datasheet www.3alogics.com | confidential 69 13.3 standard i/o pin dc characteristics symbol parameter min max conditions vdd ?? vil low level input voltage -0.5v 0.3 x vdd 2.7v to 3.6v guaranteed input low voltage vih high level input voltage 0.7 x vdd vdd + 0.5v 2.7v to 3.6v guaranteed input high voltage vol low level output voltage vss + 0.1v 2.7v voh high level output voltage vdd C 0.1v 2.7v 13.4 schmitt trigger input threshold vt+ vt- hysteresis unit min max typ min max typ min max typ 1.39 2.06 1.82 0.9 1.46 1.24 0.49 0.6 0.58 v
TRH031M datasheet 13.5 timing specification 13.5.1 timing for read/write strobe symbol parameter min max unit t lhll pale pulse width 10 ns t avll multiplexed address bus setup time 4 ns t llax multiplexed address bus hold time 6 ns t llwl pale low to wrb, rdb low 5 ns t clwl csb low to wrb, rdb low 0 ns t whch wrb, nwr high to csb high 0 ns t rldz rdb low to data valid 35 ns t rhdz rdb high to data high impedance 20 ns t wldv wrb low to data valid 35 ns t whdx data bus hold time 6 ns t wlwh wrb, rdb pulse width 41 ns t avwl separated address bus setup time 5 ns t whax separated address bus hold time 6 ns t whwl period between sequenced r/w accesses 150 ns 70 ww.3alogics.com confidential | w pale wrb rdb csb data addr multiplexed addressbus databus separated addressbus t lhll t clwl t whch t wlwh t llax t avll t avw l t whax t whwl t llwl t whwl t whdx t rhdz t wldv t rldv picture 13-1 timing for sep arated read/write strobe
TRH031M datasheet www.3alogics.com | 13.5.2 timing for spi compatible interface symbol parameter min max unit t sckl sck low pulse width 100 ns t sckh sck high pulse width 100 ns t shdx sck high to data changes 20 ns t dxsh data changes to sck high 20 ns t sldx sck low to data changes 15 ns t slnh nss miso mosi sck t sckl msb msb lsb lsb t sckh t sckl t shch t sldx t dxsh t shdx t dxsh picture 13-2 timing for spi compatible interface confidential 71 sck low to nss high 20 ns
TRH031M datasheet 13.6 package information 7.00 0.20 9.00 0.30 # 32 # 1 72 ww.3alogics.com confidential | w 0.80 0.30 0.10 0.10 max (0.70) 0.127 +0.10 -0.05 0-8 0.10 max 0.50 0.20 picture 13-3 32-pin lqfp package dimemsion
TRH031M datasheet www.3alogics.com | 3alogics 13.56mhz muti-protocol rfid reader ic data sheet it?s rfid rfid & mobile soc for ubiquitous technology tel : (82) C (31) C 715 C 7117 fax : (82) C (31) C 719 C 7551 homepage : http://www.3alogics.com email : rfid@3alogics.com 7 th floor, hyundai-of fice bldg., 9-4, sunae-dong. bundang-gu, seongnam-si, gyeonggi-do,463-783,korea confidential 73

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